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The measurement results validate the analysis and simulation results well.Ī.F. The proof-of-concept prototypes are designed in a 0.18- \(\upmu \)m CMOS process, and a 3-stage PGA with ADCOC is fabricated. The transistors with a longer channel length are preferred for their lower thermal and flicker noise current. For a digital DCOC (DDCOC), the extra noise comes from the transistors of the current source (sink) bank. We propose an optimization technique that can effectively alleviate the noise issue by increasing the feedback amplifier’s gain and the resistor’s value simultaneously, while maintaining a reasonable DC gain. For an analog DCOC (ADCOC), it is concluded that the PGA’s noise increases rapidly as the output DC offset decreases, thereby causing difficulties to achieve both low noise and low DC offset simultaneously. The analysis presented shows that the DCOC-induced noise may deteriorate the PGA’s noise performance significantly if we do not pay enough attention to it. The noise contribution of a DC offset cancelation (DCOC) circuit in a programmable gain amplifier (PGA) is studied for the first time in this paper.
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